A simple interface for the purpose of data transfer between integrated circuit devices will often include a clock signal provided by the host device which is used by the slave device to output data to the host. A specific example is a read cycle of a memory card or other memory device by a host. The timing of the data output from the slave is then dependent on the arrival of the clock signal. There is an ongoing process to increase of performance of such devices. When higher transfer speeds are desired, one approach is to migrate an interface protocol to a source-synchronous scheme where the both the clock and data signals are provided from the same device, such as in a DDR (Double Data Rate) arrangement used in DRAM devices. However, this approach may not be practical to use in many devices as it may incur substantial changes to the interface (e.g. addition of signal pins). Consequently, there is room for improvements in such interfaces.